A Sacrificial Metal Layer (SML) is used to
interconnect die clusters on the wafer and provide an interface between the wafer and the test hardware.
The SML is designed to make contact with the die power (core
and I/O), the DFT interface and to provide multiplexed output
monitoring. Several die are grouped into clusters which, via isolation
resistors and fusible links, will share the same inputs. All
passive components and cluster buss routing will be placed within
the scribe lines on the wafer. The SML is placed above the wafer
passivation layer and
is added post wafer processing, typically in a bump facility. If the
die are being manufactured as KGD the SML would be removed after testing has been
completed.
In some instances active components
for die output multiplexing may be designed into the active device
layers for inclusion during the wafer processing.