Burn-in is a test method used to stress
integrated circuits (IC's) to provide a high level of performance
reliability when
included in completed assemblies. A number of IC's are loaded onto a
test fixture which is mounted into a chamber capable of reaching
stress temperatures of 150°C. All the IC's on the test fixture are
exercised using stimulus vectors designed to maximize toggle rates. To date most burn-in has been
performed on packaged devices as part of the back-end test process.
The burn-in cycle allows for detection of early-life failures (ELF)
and provides end of life data. During the burn-in cycle the devices are transferred to automated
test systems (ATE) for electrical verification. As the industry
moves towards a requirement for known-good-die (KGD) it is becoming
necessary to find alternate methods of burn-in which can be used at
the wafer level. This will ultimately lead to the burn-in step being
integrated into the front-end test path, providing direct process
control feedback to the foundries, allowing qualification data to be
gathered and processed early in the design cycle, and will reduce
the overall test cost associated with burning-in at the package
level.