As the industry moves towards KGD and multi-chip modules there is an increasing need for burn-in systems capable of performing the burn-in test function at the wafer level. These wafer level burn-in systems are being designed around several driving factors:

Process Control Feedback to the FAB
The WLBT system can be used to perform process control feedback by running 'test wafers' along with the production run. These 'test wafers' can be designed to include several hundred product die along with test sets designed specifically to qualify the manufacturing process.

Early Life Failure (ELF) Data
The 'test wafers' would allow ELF data feedback within hours of manufacture rather than weeks if packaged burn-in is used. Since the 'test wafers' are discarded after use, the process step for removing the sacrificial metal layer is not required.

Need for Known Good Die (KGD)
KGD required for multi-chip modules and system-on-chip (SOC) packages. WLBT eliminates the need for special chip carriers to heat and test bare die so providing a cost effective solution.

Reliability Test Screening
For ≤0.18 micron process, Iddq measurements are problematic and unsuitable for KGD reliability test screening. WLBT eliminates the need to perform this type of testing.

Cost savings
WLBT catches early life failures (ELF) in marginal and defective devices before wafers reach final packaging and test. WLBT performed using DFT structures can dramatically reduce the need for automated test equipment (ATE). Reducing the use of expensive ATE and catching ELF’s prior to packaging can result in cost savings of more than 50% when volumes exceed one million units per year ¹. WLBT can decrease or eliminate costs associated with package level burn-in.

Test During Burn-In (TDBI) technology
An increasing proportion of bare die have higher complexity and speed. Many devices are now having DFT features built in.

A cost-effective interface between wafer and test hardware
Alignment between wafer and contactor is critical to the test process. I/O fan out, small die pitch, circuitry routing all need to be considered when developing test circuitry.

Electrical requirements
Die isolation is essential to perform effective testing. Power dissipation per wafer can be in the 1-2kW range. BIST allows the die to operate at speeds beyond package level burn-in, so increasing the need for efficient current management.

Thermal management
Hot/Cold testing (-55ºC to +180ºC).

¹ Study conducted by Austin-based Microelectronics and Computer Technology Corp.

While there are several potential solutions in development, Delta V Instruments has a proven platform, currently being used in a production environment by a leading microprocessor manufacturer. This platform makes use of a ‘sacrificial metal’ technique for interconnection and a ‘clustering’ scheme to limit the number of I/O lines required for test. This minimizes the need for full point to point contact directly onto the wafer. By taking this approach the customer greatly reduces the costs associated with custom test fixtures and eliminates potential wafer damage or false failure reporting due to misalignment of a full contact solution.

Our stimulus hardware makes full use of all DFT features built into the device under test. When used in conjunction with wafer level integrated test chip technology our solution to WLBT ensures a high volume throughput with high visibility testing and feedback monitoring for both qualification and production applications.

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